Apparatus for driving output signals from DLL circuit

ABSTRACT

Disclosed is an apparatus for driving output signals of a DLL circuit. The apparatus includes a first driving part and a second driving part for receiving output signals of the DLL circuit, wherein the DLL circuit is employed for a synchronous memory device, an output signal of the first driving part controls a data output driver of the synchronous memory device, and an output signal of the second driving part controls an ODT circuit of the synchronous memory device.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an apparatus for driving output signalsfrom a DLL circuit, and more particularly to an apparatus for drivingoutput signals from a DLL circuit, which has at least two driving partsfor receiving the output signals from the DLL circuit.

2. Description of the Prior Art

As generally known in the art, a delay locked loop (DLL) circuitcontrols output timing of data read out from a synchronous memory device(hereinafter, referred to as “memory device”) on the basis of a clockexternally applied to the memory device.

FIG. 1 is a block diagram showing a structure of a typical DLL circuit100 by way of example.

As shown in FIG. 1, the DLL circuit 100 includes clock buffers 11 and12, a delay line 13, a divider 14, a dummy delay line 15, a replicamodel part 16, a phase comparator 17, and a delay control part 18.

In FIG. 1, the clock buffers 11 and 12 receive external clocks clk andclkb. Herein, an output signal rclk of the clock buffer 11 issynchronized with a rising edge of the external clock clk, and an outputsignal fclk of the clock buffer 11 is synchronized with a rising edge ofthe external clock clkb.

The delay line 13 delays the phases of the external clocks having passedthrough the clock buffer 11.

The divider 14 divides the frequency of the external clock having passedthrough the clock buffer 12 at the ratio of 1/n (generally, n is set to‘4’ or ‘8’). Herein, the division is mainly performed in order to reducepower consumption.

The dummy delay line 15 has the same structure as the delay line 13.Herein, since the dummy delay line 15 delays a signal divided by thedivider 14, power consumption is lowered.

The replica model part 16 refers to a delay part obtained by modelingduration from application of the external clocks to arrival at the delayline 13 and duration until the output signals IRCLKDLL and IFCLKDLL ofthe delay line 13 are outputted to the outside of the memory device.

The phase comparator 17 detects a phase difference between the outputsignal of the divider 14 and the output signal of the replica model part16. If rising edges of signals applied to the phase comparator 17 arecoincident with each other, the DLL circuit is locked. At this time, theDLL clocks IRCLKDLL and IFCLKDLL lead about the length of ‘tAC’ over theexternal clocks.

The delay control part 18 controls the phases of signals applied to boththe delay line 13 and the dummy delay line 15 in response to the outputsignal of the phase comparator 17.

FIG. 2 is a view showing an operation of the conventional apparatus fordriving output signals from the DLL circuit, which employs the DLLcircuit. The circuit shown in FIG. 2 has been employed for DDR2 SDRAM,DDR3 SDRAM, etc. having the ODT circuit. For reference, a signal Rasidledenotes a signal externally applied to the memory device. The signalRasidle has a low level in an active mode and a high level in aprecharge mode. A signal ODTEN denotes a signal outputted from the EMRS.The signal ODTEN enables an operation of the ODT.

As shown in FIG. 2, the output signal of the DLL circuit issimultaneously applied to both an ODT circuit 230 and an output driver240 through a driving part 210.

Accordingly, conventionally, even when only the ODT circuit 230 isoperated, the output driver 240 is enabled, thereby causing unnecessarypower consumption.

SUMMARY OF THE INVENTION

Accordingly, the present invention has been made to solve theabove-mentioned problem occurring in the prior art, and an object of thepresent invention is to provide a driving apparatus capable of drivingan ODT circuit and an output driver, separately.

In order to accomplish this object, there is provided an apparatus fordriving output signals of a DLL circuit, the apparatus including atleast two driving parts for receiving the output signals of the DLLcircuit, wherein output signals of each driving part are applied to acircuit part corresponding to the output signals.

An apparatus for driving output signals of a DLL circuit includes atleast two driving parts.

According to another aspect of the present invention, there is providedan apparatus for driving output signals of a DLL circuit, the apparatusincluding a first driving part and a second driving part for receivingoutput signals of the DLL circuit, wherein the DLL circuit is employedfor a synchronous memory device, an output signal of the first drivingpart controls a data output driver of the synchronous memory device, andan output signal of the second driving part controls an ODT circuit ofthe synchronous memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will be more apparent from the following detailed descriptiontaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram showing an example of a typical DLL circuit;

FIG. 2 is a view showing an operation of the conventional apparatus fordriving output signals from a DLL circuit;

FIG. 3 is a block diagram showing an apparatus for driving outputsignals from a DLL circuit according to the present invention; and

FIG. 4 is a time chart showing an operation of the apparatus shown inFIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a preferred embodiment of the present invention will bedescribed with reference to the accompanying drawings. In the followingdescription and drawings, the same reference numerals are used todesignate the same or similar components, and so repetition of thedescription on the same or similar components will be omitted.

FIG. 3 is a block diagram showing an apparatus for driving outputsignals from a DLL circuit 300 according to the present invention.

As shown in FIG. 3, the apparatus includes driving parts 310 and 330 forreceiving signals outputted from the DLL circuit 300.

The DLL circuit 300 of FIG. 3 represents all DLL circuits well known tothose skilled in the art, in addition to the conventional DLL circuitdisclosed through FIG. 1. Also, the driving part 310 and the drivingpart 330 shown in FIG. 3 include a pull-up driver and a pull-down driverwell known to those skilled in the art. Herein, it is preferred that thedriving part 310 has the same size as the driving part 330. However, thedriving part 310 may have a different size depending on loading for thenext end driven by the driving part.

As shown in FIG. 3, the operation of the driving part 310 is controlledby a control part 320 receiving signals Wt10Rbt11 and Rasidle, and theoperation of the driving part 330 is controlled by a control part 340receiving signals ODTEN and Rasidle.

The control part 320 includes an inverter 31 receiving the signalRasidle, an inverter 32 receiving the signal Wt10Rbt11, a NAND gate 33receiving output signals of both the inverter 32 and the inverter 31,and an inverter 34 receiving an output signal of the NAND gate 33. Thecontrol part 320 controls the operation of the driving part 310 by meansof an output signal EN1 of the inverter 34.

The control part 340 includes an inverter 35 receiving the signalRasidle, a NOR gate 36 receiving both an output signal of the inverter35 and an ODT enable signal ODTEN, and an inverter signal 37 forreceiving an output signal of the NOR gate 36. Herein, the operation ofthe driving part 330 is controlled by an output signal EN2 of theinverter 37. Herein, those skilled in the art can realize variouscircuits performing functions identical to those of the control parts320 and 340.

Output signals IRCLKDLL and IFCLKDLL of the driving part 310 are appliedto a data output driver 350 of a synchronous memory device so as toadjust a data output time point of the data output driver 350. Inaddition, output signals IRCLKDLLOE and IFCLKDLLOE of the driving part330 are applied to an ODT circuit 360 of the synchronous memory devicein such a manner that an impedance calibration operation may beperformed. Since the driving parts 310 and 330 independently operate,the output driver 350 and the ODT circuit 360 (controlled by the outputsignals of the driving parts 310 and 330, respectively) independentlyoperate also. Therefore, power consumption may be reduced as comparedwith the conventional apparatus for simultaneously driving an outputdriver and an ODT circuit.

Hereinafter, description about the operation according to one embodimentof the present invention disclosed through FIG. 3 will be given indetail.

First, the meanings of the signals shown in FIG. 3 will be described.

The signal Wt10Rbt11 represents a write mode or a read mode. The signalWt10Rbt11 maintains a high level in a write mode and a low level in aread mode.

The signal Rasidle is externally applied to the memory device. Thesignal Rasidle maintains a low level in an active mode and a high levelin a precharge mode.

The signal ODTEN is outputted from the EMRS and enables the ODToperation.

Hereinafter, the operations of the control part 320 and the driving part310 will be described.

When the signal Rasidle (row address select idle) is in a low level(i.e., an active mode) and the signal Wt10Rbt11 is in a high level(i.e., a write mode), the output signal EN1 of the control part 320 isin a low level. Accordingly, the driving part 310 and the data outputdriver 350 are disabled. Therefore, in a write mode, it is possible toreduce current consumption in both the driving part 310 and the dataoutput driver 350.

When the signal Rasidle is in a low level (i.e., an active mode) and thesignal Wt10Rbt11 is in a low level (i.e., a read mode), the outputsignal EN1 of the control part 320 is in a high level. Accordingly, thedriving part 310 and the output driver 350 are enabled.

When the signal Rasidle is in a high level (i.e., a precharge mode), thedriving part 310 and the output driver 350 are always disabled. That is,in a precharge mode, it is possible to reduce current consumption in thedriving part 310 and the output driver 350.

Hereinafter, the control part 340 and the driving part 330 will bedescribed.

If the signal ODTEN (on-die termination enable) for performing an ODT(on-die termination) operation is outputted from the EMRS (extended moderegister set), the ouput signal EN2 of the control part 340 is always ina high level regardless of the value of the signal Rasidle. Accordingly,the driving part 330 and the ODT circuit 360 are enabled.

When the signal ODTEN is in a low level, the output signal EN2 of thecontrol part 340 is determined by the signal Rasidle. That is, if thesignal Rasidle is in a high level (in a precharge mode), the drivingpart 330 and the ODT circuit 360 are disabled. If the signal Rasidle isin a low level (in an active mode), the driving part 330 and the ODTcircuit 360 are enabled.

FIG. 4 is a time chart for explaining the operation according to thepresent invention.

As understood from FIG. 4, during the high level of the signal ODTEN,the driving part 330 delivers the signal received from the DLL circuit330 to the ODT circuit 360.

Meanwhile, it can be understood that the driving part 310 is disabled ina write mode and is enabled in a read mode regardless of the signalODTEN.

Although two driving parts are included in the apparatus shown in FIGS.3 and 4, at least three driving parts may be included according to thespirit of the present invention.

In addition, the spirit of the present invention can be applied to allsemiconductor devices using DLL circuits in addition to memory devices.

When the spirit of the present invention is employed, a driving part forreceiving the output signal of the DLL circuit is independentlyoperated, thereby reducing power consumption as compared with theconventional apparatus.

Although a preferred embodiment of the present invention has beendescribed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the inventionas disclosed in the accompanying claims.

1. An apparatus for driving output signals of a DLL (delay locked loop)circuit, the apparatus comprising: a first driving part and a seconddriving part for receiving output signals from the DLL circuit, whereinthe DLL circuit is employed by a synchronous memory device, an outputsignal of the first driving part controls a data output driver of thesynchronous memory device, and an output signal of the second drivingpart controls an ODT (on-die termination) circuit of the synchronousmemory device.
 2. An apparatus for driving output signals of a delaylocked loop (DLL) circuit in which the DLL circuit is employed by asynchronous memory device, the apparatus comprising: a first drivingpart and a second driving part for receiving output signals of the delaylocked loop DLL circuit, an output signal of the first driving partcontrols a data output driver of the synchronous memory device, and anoutput signal of the second driving part controls an on-die termination(ODT) circuit of the synchronous memory device, wherein the firstdriving part is disabled if the synchronous memory device is in aprecharge mode or in a write mode, the first driving part is enabled ifthe synchronous memory device is in a read mode, the second driving partis enabled if the synchronous memory device is in an ODT operation mode,and the second driving part is disabled if the synchronous memory deviceis not in the ODT operation mode.
 3. The apparatus as claimed in claim2, wherein the first diving part and the second driving partindependently operate from each other.
 4. The apparatus as claimed inclaim 2, wherein the second driving part is enabled in an active modeand disabled in a precharge mode.
 5. An apparatus for driving outputsignals of a delay locked loop (DLL) circuit in which the DLL circuit isemployed by a synchronous memory device, the apparatus comprising: afirst driving part operatively configured to the DLL circuit to receiveoutput signals from the DLL circuit; a first control part operativelyconfigured to the first driving part to send output signals from thefirst control part to control the first driving part; a second drivingpart operatively configured to the DLL circuit to receive output signalsfrom the DLL circuit; and a second control part operatively configuredto the second driving part to send output signals from the secondcontrol part to control the second driving part, wherein the first andsecond driving parts operate independent from each other.
 6. Theapparatus of claim 5 further comprising: a data output driveroperatively configured to the first driving part to receive outputsignals from the first driving part; and an on-die termination (ODT)circuit operatively configured to the second driving part to receiveoutput signals from the second driving.
 7. The apparatus of claim 6wherein the first control part operatively configured to receive a rowaddress select idle (Rasidle) signal and a write/read (Wt10Rbt11)signal.
 8. The apparatus of claim 7 wherein when the Rasidle signal isin a state associated with a precharge mode then the first control partand the data output driver are operatively configured to be disabled. 9.The apparatus of claim 7 wherein when the Rasidle signal is in a stateassociated with an active mode and the Wt10Rbt11 signal is in a stateassociated with a write mode then the first control part and the dataoutput driver are operatively configured to be disabled.
 10. Theapparatus of claim 7 wherein when the Rasidle signal is in a stateassociated with an active mode and the Wt10Rbt11 signal is in a stateassociated with a read mode then the first control part and the dataoutput driver are operatively configured to be enabled.
 11. Theapparatus of claim 6 wherein the second control part operativelyconfigured to receive a row address select idle (Rasidle) signal and anon-die termination enable (ODTEN) signal.
 12. The apparatus of claim 11wherein when the ODTEN signal is in a state associated with an enablemode then the second control part and the ODT circuit are operativelyconfigured to be enabled.
 13. The apparatus of claim 11 wherein when theODTEN signal is in a state associated with an unenable mode and theRasidle signal is in a stats associated with an precharge mode then thesecond control part and the ODT circuit are operatively configured to bedisable.
 14. The apparatus of claim 11 wherein when the ODTEN signal isin a state associated with an unenable mode and the Rasidle signal is ina state associated with an active mode then the second control part andthe ODT circuit are operatively configured to be enabled.
 15. Theapparatus of claim 11 wherein the ODTEN signal is outputted from anextended mode register set (EMRS).
 16. The apparatus of claim 6 whereinthe first control part comprising a first inverter having an input andan output, wherein the input of the first inverter operatively connectedto receive the Rasidle output signal; a second invader having an inputand an output, wherein the input of the second inverter operativelyconnected to receive the Wt10Rbt11 signal; a NAND gate having a firstand second input and an output, wherein the first input of the NAND gateoperatively connected to an output of the first inverter and the secondinput of the NAND gate operatively connected to an output of the secondinverter; a third inverter having an in put and an output, wherein theinput of the third inverter operatively connected to the output of theNAND gate and the output of the third inverter operatively connected tothe first driving part.
 17. The apparatus of claim 6 wherein the secondcontrol part comprising: a first inverter having an input and an outputwherein the input of the first inverter operatively connected to receivethe Rasidle output signal; a NOR gate having a first and second inputand an output, wherein the first input of the NOR gate operativelyconnected to the output of the first inverter, and the second input ofthe NOR gate operatively connected to receive the ODTEN signal; and asecond inverter having an input and an output wherein the input of thesecond inverter operatively connected to the output of the NOR gate, andthe output of the second inverter operatively connected to the seconddriving part.